Coupled variable‐input LCG and clock divider‐based large period pseudo‐random bit generator on FPGA
نویسندگان
چکیده
منابع مشابه
A Pseudorandom Bit Generator based on Chaotic Coupled Map Lattices
In this paper, we discuss the properties of making a deterministic algorithm suitable to generate a pseudo random sequence of numbers: high value of Kolmogorov-Sinai entropy, high dimensionality of the parent dynamical system, and very large period of the generated sequence. We propose the chaotic coupled map lattices as a pseudo random number generator. We show what chaotic features of the cou...
متن کاملA Pseudorandom Bit Generator Based on Block Upper Triangular Matrices
The popularity of the Web has created a great marketplace for businesses to sell and showcase their products increasing the need for secure Web services such as SSL, TLS or SET. We propose a pseudorandom bit generator that can be used to create a stream cipher directly applicable to these secure systems; it is based on the powers of a block upper triangular matrix achieving great statistical re...
متن کاملA Multi Maximal Length Multi Time Period Pseudorandom Bit Sequence (PRBS) Generator
A novel method of generating a pseudorandom binary sequence (PRBS) test signal generator is presented. A traditional PRBS generator uses a linear feedback shift register (LFSR) which generates a single maximum length sequence pattern having a fixed period. In this paper, three shift registers with feedback connections are employed in which the preset inputs of the shift registers are changed on...
متن کاملA Symmetric Differential Clock Generator for Bit-Serial Hardware
Bit-serial architectures require less area but more sophisticated clocking mechanisms than their parallel counterparts. This paper presents a CMOS circuit that generates high-frequency clock waveforms for bitserial hardware. Triggered by a master clock input, the circuit outputs a fixed number of pulses followed by a completion signal. The design uses two coupled ring oscillators to produce dif...
متن کاملFPGA acceleration of a pseudorandom number generator based on chaotic iterations
As any well-designed information security application uses a very large quantity of good pseudorandom numbers, inefficient generation of these numbers can be a significant bottleneck in various situations. In previous research works, a technique that applies welldefined discrete iterations, satisfying the reputed Devaney’s definition of chaos, has been developed. It has been proven that the gen...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: IET Computers & Digital Techniques
سال: 2021
ISSN: 1751-8601,1751-861X
DOI: 10.1049/cdt2.12027